Those skilled in the art will recognize that a technology node (also referred to as a process node) is typically identified in nanometers (e.g., a 45 nm, 32 nm, 22 nm, 14 nm, etc.), thereby indicating the size of the semiconductor features that can be formed on a wafer using the technology. The technology node may also indicate the type of wafer, such as a silicon-on-insulator (SOI) wafer (e.g., 45 nm SOI, 32 nm SOI, 22 nm SOI, etc.). In any case, each technology node is associated with sets of design rules (also referred to as sets of ground rules, rule decks, run sets, etc.) that are incorporated into a process design kit (PDK) and applied during particular stages in the design flow (e.g., at power planning, at input/output pin placement, at library element placement, at clock planning, at wire routing, etc.) in order to ensure optimal manufacturability (i.e., in order to ensure that the intended functionality of an IC design can be achieved with a high degree of yield). Such design rules can, for example, include geometric constraints (also referred to as tolerances) on the mask patterns used at the various levels of an IC design layout. That is, such design rules can place constraints on the mask patterns used at each level both individually and in combination with the mask patterns in the levels above and/or below. Thus, the design rules for a technology node can include intra-level rules that specify minimum and maximum shape length, width and overall area, minimum and maximum spacing between shapes, allowable shape orientations, etc. The design rules for a technology node can also include inter-level rules that specify the minimum and maximum distance between shapes in different levels, minimum and maximum overlay, etc. Unfortunately, as device sizes continue to decrease and device density continues to increase with each new technology node, techniques for accurately determining the optimal design rules are becoming ever more difficult and time-consuming.